The RTL9603C is an integrated System-on-a-Chip (SoC) Application Specific Integrated Circuit (ASIC)

with dual CPU MIPS interAptiv™ and RLX5281, that implements L2 switch functions and Layer 3/4

hardware NAT/NAPT. The RTL9603C integrates an RLX5281 processor with clock rate up to 500MHz

deal with VoIP. Both support the MIPS interAptiv™ with clock rate up to 950Mhz deal with system,

WIFI, switch and USB etc.A standard 5-signal P1149.1 compliant EJTAG test interface is supported for

CPU testing and software development.

Via table configuration and look-up, the RTL9603C can perform hard-wired network traffic forwarding.

The CPU may be used to handle upper layer functions, such as DHCP, HTTP, and some other protocols,

and to operate with a hard-wired forwarding engine.

The RTL9603C integrates one Gigabit Ethernet physical layer transceivers for 10Base-T, 100Base-TX,

and 1000Base-TX, three Fast Ethernet physical layer transceivers for 10Base-T, 100Base-TX, and one

SerDes interface type to work with an external PON transceiver.

The RTL9603C supports flexible IEEE 802.3x full-duplex flow control and optional half-duplex

backpressure control. For full-duplex, standard IEEE 803.3x flow control will enable pause ability only

when both sides of UTP have auto-negotiation ability and have enabled pause ability. The RTL9603C

also provides optional forced mode IEEE 802.3x full-duplex flow control. Based on optimized packet

memory management, the RTL9603C is capable of Head-Of-Line blocking prevention.

Due to its powerful protocol parser, the RTL9603C can recognize and hard-wire-forward VLAN-tagged,

SNAP/LLC, PPPoE, IP, TCP, UDP, ICMP and IGMP packets. Layer 2, 3, and 4 information is stored in

look-up tables. For VLAN and PPPoE protocols, the RTL9603C can automatically encapsulate and

decapsulate VLAN tagged frames and PPPoE headers.

The RTL9603C supports port-based, protocol-based, and tagged VLANs. Up to four thousand VLAN

groups can be assigned. VLAN tags are inserted or removed based on the VLAN table configuration. The

spanning tree protocol is supported and the states are divided into four types: Disabled,

Blocking/Listening, Learning, and Forwarding.

For peripheral interfaces, two 16550-compatible UARTs,and one high speed uart are supported.

The RTL9603C requires only a single 25MHz crystal clock input for the system PLL. The RTL9603C

also has nine hardware timers and one watchdog timer to provide accurate timing and watchdog

functionality. For extension and flexibility, the RTL9603C has up to 35 GPIO pins.

The RTL9603C is provided in a LQFP-128 package.